A typical line card used in optical networking equipment consists of multiple modules for translating network packets into a format suitable for transmission over the optical media. In a synchronous optical network/synchronous digital hierarchy (“SONET/SDH”) system, the translation components consist of a framer device for translation between data packets and SONET/SDH frames, a serializer/deserializer (“SERDES”) component for conversion of the parallel data-and-clock input/output of the framer to the self-clocking serial data required for transmission, and a transceiver that performs the electrical/optical conversion and the optical transmit/receive function. FIG. 1 diagrammatically illustrates the components of a conventional line card 130 in accordance with the known art.
As illustrated in FIG. 1, there are two (2) electrical interfaces within a SONET/SDH based communication system: system packet interface (“SPI”) 110 and SERDES framer interface (“SFI”) 120. SPI 110 is the electrical interface between physical layer (“PHY”) 130 and link layer 107 which communicates with the rest of system 105. SPI 110 separates synchronous PHY 130 from the asynchronous packet-based processing performed by the higher layers of system 105. SPI 110 supports transmit and receive data transfers at clock rates independent of actual line bit rates. It is designed for the efficient transfer of both variable-sized packet and fixed-sized cell data. SFI 120 defines an electrical interface between SONET/SDH framer 135 and the high-speed logic of SERDES 140. SERDES 140 serializes (parallel-to-serial) and de-serializes (serial-to-parallel) data. SFI 120 permits SERDES 140 and framer 135 to be implemented in different speed technologies. In practice, the framer 135 to SERDES 140 interface (SFI 120) is often referred to as the framer-to-transceiver interface due to the frequent combination of SERDES 140 and transponder components 145 into a single module 150. Both SPI 110 and SFI 120 can provide a standard interface to internal networking components. This standardization of PHY 130 leads to lower costs. Because of evolving transmission speeds and technology enhancements, a number of different variations of these electrical interfaces have been defined, such as SPI-3, SPI-4, SFI-4 and SFI-5.
In the case of the SFI-4 specification, the framer-to-SERDES interface is optimized for the pure transfer of data. There is no protocol, or framing, involved in data transfers. An SFI-4 interface can include a 16-bit wide data bus with each channel operating at 622 MHz. With a maximum bus bandwidth of 12.12 Gbps, SFI-4 can support the optical carrier (“OC”) data rate, OC-192. FIG. 2 diagrammatically illustrates a conventional SFI-5 interface 121 in accordance with the known art. An SFI-5 interface includes a 16-bit wide data bus with each channel operating at up to 3.125 Gbps. SFI-5 has a maximum bus bandwidth of 50 Gbps and can support the OC-768 data rate, which is currently the fastest SONET data transmission rate.
Single-chip interface converters are being developed to support optical networking applications that use both 10 Gbps and 40 Gbps data rates. These single-chip converters provide standards-based products that enable service providers to cost-effectively transition to higher data rates while preserving legacy system applications. This allows service providers to leverage existing 10 Gbps components with SFI-4 interfaces while deploying 40 Gbps systems with SFI-5 interfaces.
Referring to FIG. 3, an OC-768 frame 310, such as that used by an SFI-5 interface, includes four (4) OC-192 frames 315, multiplexed 64 bytes at a time as shown at 320. Interface converter 350 is primarily a MUX/DEMUX device that operates as a translator, transforming signals between the high-speed (SFI-5) side and the low-speed (SFI-4) side. The data stream of an SFI-4 interface is striped across four (4) ports 325. This is diagrammatically illustrated in FIG. 3, portions of which are described in greater detail below with reference to FIG. 4.
When OC-768 SONET frames are converted from SFI-5 format to SFI-4 format, it is extremely difficult to prove frame integrity at the output using existing OC-192 transponders. This is because the 4×16 data lanes at 31 are still multiplexed and may be skewed with respect to one another. Additionally, extracting 64 bytes per OC-192 frame though a field programmable gate array (“FPGA”) is not realistic, as the extraction timepoint is not defined. Currently, OC-768 transponders are not available. Even if they were, the 4×16 data lanes may still be skewed with respect to one another and therefore could not be fed “as-is” to the transponder. The conversion verification between SFI-4 and SFI-5 in a single-chip interface converter currently requires connecting the converter to a framer and then validating the output of the framer, which has OC-192 frames, bifurcated per port. This involves communication between two (2) chips and increases the difficulty of problem isolation.
It is therefore desirable to provide a solution that enables interface conversion verification with a single chip and improves problem isolation. Exemplary embodiments of the present invention can provide this by modifying the input data pattern (e.g., creating a 40G, or pseudo OC-768, frame by multiplexing four OC-192 frames, two bytes at a time) to provide per port demultiplexing of data streams at the output of the interface converter.